1. Field of the Invention
The present invention relates to a DRAM cell capacitor and, more particularly, to a method for fabricating a DRAM cell capacitor having HemiSpherical Grain (HSG) silicon on a storage node, wherein a bottom portion thereof has no HSG so as to prevent electrical bridges between adjacent storage nodes.
2. Description of the Related Art
Recent advances in the miniaturization of integrated circuit devices, such as high density DRAMs, have reduced the wafer area available for each individual memory cell. Yet, even as the footprint (an area of a silicon wafer allotted for individual memory cells) shrinks, the storage node must maintain a certain minimum charge storage capacity, determined by design and operational parameters to ensure reliable operation of memory cell. It is thus increasingly important that capacitors have a high charge storage capacity per unit area of the wafer. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the wafer area occupied by the cell.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An inter-electrode dielectric material is deposited between two conductive layers that form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance. C=∈ ∈0 A/d, where ∈ is the dielectric constant of the capacitor dielectric, ∈0 is vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance include the use of new materials having high dielectric constants.
Other techniques have focused on increasing the effective surface area (xe2x80x9cAxe2x80x9d) of the electrodes by modifying the surface morphology of the polysilicon storage electrode itself engraving or controlling the nucleation and growth condition of polysilicon. An HSG polysilicon layer can be deposited over a storage node to increase a surface area and capacitance.
U.S. Pat. No. 5,623,243 by Watanabe et al. entitled as xe2x80x9cSEMICONDUCTOR DEVICE HAVING POLYCRYSTALLINE SILICON LAYER WITH UNEVEN SURFACE DEFINED BY HEMISPHERICAL OR MUSHROOM LIKE SHAPE SILICON GRAINxe2x80x9d is incorporated herein by reference. U.S. Pat. No. 5,741,734 by Young Jung Lee, U.S. Pat. No. 5,634,974 by Ronald A et al., U.S. Pat. No. 5,798,298 by Kiyoshi Mori et al., the disclosures of which are incorporated by reference herein, discloses capacitors with rough surface morphology.
Conventional methods for fabricating a DRAM cell capacitor with HSG silicon are described as follows: depositing a storage electrode layer; patterning the storage electrode layer to form a storage electrode; forming an HSG silicon layer; forming a dielectric layer such as Ta2O5; forming a plate electrode layer; and patterning the plate electrode layer.
If a design rule of 0.15 micrometers or less is used, a polysilicon layer for the storage node must be formed thick to obtain a desired capacitance in a given cell area. The patterning of such thick polysilicon layer is very difficult and causing a problem associated with slope etching. As schematically illustrated in FIG. 1, an electrical bridge at the bottom portion of the patterned storage node can be generated due to a polysilicon tail (see reference number 22) caused by slope etching. Furthermore, when HSG silicon is formed on the patterned polysilicon layer (i.e., storage node), aforementioned electrical bridge can be generated extensively (see reference number 23).
Accordingly, overetching is required to remove the polysilicon tail. Such overetching can make the neck portion of the resulting storage node thin (see reference number 24 of FIG. 2) when misalignment can occurs. In severe cases, the storage node may fall down.
Accordingly, there is a strong need for a method for fabricating a DRAM cell capacitor with increased surface areas without causing an electrical bridge and falling down of the storage node.
The present invention was made in view of the above problems, and the present invention is directed toward providing a method for fabricating a DRAM cell capacitor with HSG silicon on its surface.
One of the features of the present invention is the formation of a storage node having a double layer structure. The bottom layer of the storage node is made of polysilicon that suppresses the growth of HSG seeds. Alternatively, the bottom layer can be formed of an amorphous silicon layer. Then, an annealing process is performed in order to transform the amorphous silicon layer into a polysilicon layer so as to suppress the growth of HSG seeds. The top layer of the storage node is made of a material, such as an amorphous silicon layer, which allows the growth of the HSG seeds thereon. Accordingly, an electrical bridge between adjacent storage nodes, particularly at a bottom portion thereof, can be prevented.
The storage node has a good sidewall profile without a tail phenomenon encountered in the conventional art because the bottom layer and top layer of the storage nodes are made of different layers. Accordingly, sufficient overetching can be implemented so that no electrical bridge at the bottom portion of the storage node can be formed.
In accordance with the present invention, the capacitor is comprised of a stacked storage node having a double layer structure, a dielectric film and a plate node. The staked storage node is made of a bottom layer and a top layer. The bottom layer is made of a material that suppresses the growth of HSG seeds. The bottom layer is formed to a thickness of about 1,000 angstroms to about 2,000 angstroms. For example, the bottom layer is made of polysilicon. Also, the bottom layer can be made of amorphous silicon that is annealed subsequently in order to prevent the growth of HSG seeds thereon. The top layer of the storage node is formed of a material that allows the growth of HSG seeds thereon. Therefore, HSG silicon is formed on the top layer. The top layer is formed to a thickness greater than the thickness of the bottom layer. For example, the top layer is formed to a thickness of about 8,000 angstroms to about 10,000 angstroms.
According to the present invention, the stacked capacitor is provided by forming an interlayer insulating layer on a semiconductor substrate. The semiconductor substrate includes a transistor thereon. The transistor is comprised of a gate electrode, a capping layer, sidewall spacers and source and drain regions. The transistor and the semiconductor substrate are electrically insulated by a gate oxide layer disposed therebetween.
Selected portions of the interlayer insulating layer are etched to form contact holes for contacting one of the source and drain regions. A first conductive material for the bottom layer of the storage node is deposited in the contact hole and on the interlayer insulating layer. The first conductive material suppresses the growth of HSG seeds. The deposited first conductive material is then planarized. The planarized first conductive material on the interlayer insulating layer has a thickness of about 1,000 angstroms to about 2,000 angstroms. Using a photolithographic process, the planarized first conductive material is patterned to form a first conductive pattern to be electrically connected to one of the source and drain regions. This first conductive material is formed of polysilicon. A second conductive layer is formed on the resulting structure. The second conductive layer is then patterned to form a second conductive pattern, defining the staked storage node together with the underlying first conductive pattern. The second conductive pattern is formed of a material that allows the formation of HSG seeds. For example, amorphous silicon may be used. Subsequently, an HSG silicon layer is formed only on the second conductive pattern through HSG seeding and growing by heat treatment.
A dielectric film and a plate node are sequentially deposited on the resulting structure to form a capacitor.
In the above method, the first conductive material may be formed of amorphous silicon. In this case, the deposited amorphous silicon layer needs to be transformed into a crystalline structure, i.e.,a polysilicon layer so as to suppress the growth of HSG seeds. For this purpose, an annealing process may be carried out in a nitrogen ambient at a temperature of about 750xc2x0 C. for about 10 minutes. Such an annealing process can be carried out at any time after the deposition of the first conductive material and before the deposition of the second conductive layer. By forming an HSG silicon layer only on a top portion, not on the bottom portion of the storage node, the surface area of the storage node be increased and the electrical bridge at the bottom portion can be inherently prevented.
Alternatively, the planarization of the first conductive material can be carried without leaving the first conductive material on the interlayer insulating layer. Namely, a contact plug is formed using a planarization process. Then, another conductive material, which suppresses the growth of HSG seeds, is deposited to a thickness of about 1,000 angstroms to about 2,000 angstroms and patterned to be electrically connected to the contact plug. A second conductive material is then deposited and patterned to form a second conductive pattern. The second conductive pattern, together with the underlying conductive material pattern, defines the storage node. Subsequently, an HSG silicon layer is formed only on the second conductive pattern using a conventional method.